1. Field of the Invention
This invention relates generally to data addressing and, more specifically, to a processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating bank address values and method therefor.
2. Description of the Prior Art
Generally speaking, a processor is an entity where a central processing unit (CPU) is present and is used to fetch and execute stored instructions or microcode. Some examples of processors are microcontrollers, microprocessors, and digital signal processors. Each type of processor operates on data which is also commonly referred to as operands. This data is generally stored in registers or memory space.
In many processor architecture schemes, adding or changing addressing modes is extremely difficult. Without major changes to the instruction set organization, such changes and additions to the addressing modes are not possible. However, changes to the instruction set structure is not desirable since many tools such as assemblers and compilers will also require dramatic changes.
Some current processor architectures use a paging scheme to address all of the data memory in the processor. In addition to the problems stated above, these types of processors have several other problems associated with them. In order to increase addressable address space, many processors implement multiple banks in their data memory. However, these processors only have one source for generating bank address values, the bank select register. Since there is only one source for generating bank address values, any instruction that needs to be executed has to access a register address in the current bank. If the instruction needs to access a register address in a different bank, the value in the bank select register has to be changed. This scheme is extremely cumbersome in that it takes several instructions to make sure the user is writing or reading the proper address in the RAM.
These types of processors also complicate the job of the C-compiler because the C-compiler must keep track of which bank is currently selected in the data memory. This presents even more problems when handling interrupts. When handling interrupt requests, the processor must have direct access to general and special function registers. If these registers are not in the currently selected bank, the bank select register must be changed to the proper bank. Once the interrupt request has been serviced, the processor must remember and return to the bank and register of the instruction being executed by the processor prior to the interrupt.
Therefore, a need existed to provide an improved processor architecture scheme and method therefor. The improved processor architecture scheme and method would allow for multiple addressing schemes. The improved processor architecture scheme and method would further have the ability to override the bank register in order to generate a complete data address. The improved processor architecture scheme and method would also allow for the processor to handle interrupt request without changing the bank select register and thus the bank address value of the current instruction being executed prior to the interrupt request.